The present invention relates to arrays of NANO-electronic devices.
The success of the PC, networking, and communications-product markets has been driven largely by Moore's Law, which says that IC density doubles every 18 months. Experts predict that CMOS scaling will continue to follow Moore's Law for at least another decade, but potential bottlenecks could derail market success if not solved by new design or device technology. One of these bottlenecks is integrating precision analog and wideband RF circuitry in standard digital CMOS.
Applying Moore's Law to mixed-signal (analog and digital) chips is a significant challenge. Higher transistor density and lower silicon cost allow more complex digital circuitry, but most wireless or wireline communications products require integrating RF, analog, and memory with the digital logic. Advancements in submicron CMOS processing greatly benefit digital logic and memory, but result in poor analog and RF performance. Transistor matching, noise, resistors, capacitors, and inductors drive the density of analog circuits, and these parameters do not necessarily benefit from transistor scaling.
To compound the problem, digital-circuit design continues to benefit from advances in logic synthesis, accelerating the time-to-market of digital products. Analog circuit design has not historically benefited significantly from CAD-tool advances, and remains a hand-crafted art. Consequently, analog circuits will be a limiting factor for mixed-signal SoC, both in terms of the increasingly larger percentage of the die these circuits occupy, and in terms of their design time.